| Sponsored by |
|---|
| Altera Enixs Technologies Pvt Ltd |
| List of major Equipments: |
|---|
| Hardware |
|---|
- Altera DE1 FPGA Board - 10 Nos.
- Altera Logic Analyzer - 05 Nos.
- Altera Versatile Interface Board - 10 Nos.
- Xilinx FPGA Kits
- Xilinx CPLD Kits
- Digilent FPGA Boards
- V-Design RAPID ASIC
- Prototyping – Universal Chip Board (VRAP-UCB) (Co-simulation Using Hardware & Software)
- Virtex 7 – VC0707 Evaluation Kit
|
| Licensed Software |
|---|
- Full suite Cadence software - 15 Licences
- Quartus II Design Software - 10 Licences
- ModelSim – Altera Edition - 10 Licences
- Nios II Embedded Design Suite - 10 Licences
- Megacore IP Library - 10 Licences
- Leonardo Spectrum Synthesizer
- Place & Route Tool Level 3 – Xilinx 14.1 ISE
- VRAP Software
- Xilinx Vivado Software
|
| Capabilities |
|---|
- IC Layout Design - Analog, Digital and Mixed Signal
- Verilog / VHDL Simulation ( ASIC design off quality)
- FPGA Place & Route (Xilinx, Altera, Actel, Lucent)
- FPGA / CPLD Implementation
- Co-simulation of Hardware/Software
- Regression Testing
|
| Target Users |
|---|
- UG and PG Students
- PhD Research Scholars (Part Time & Full Time)
|
| Works done |
|---|
- FPGA / CPLD Implementation of - Gaussian Noise Generator, Programmable FIR Filter Spread spectrum Modulator, Logic Analyzer, Rake Receiver, IS-95 A Transceiver Bluetooth Transceiver, UMTS Transceivers, CPSK Baseband Decoder, OFDM Modem, Discrete Wavelet Transform, Encryption Algorithms Using Pipelining.
- FPGA Based Architecture Design - Circuit Partitioning using Genetic Algorithm and its Implementation
- FPGA Based Wireless Transceivers - IS-95A CDMA Transceivers and Wireless Home Networking Baseband Decoder
- Analytical Modelling of Dual Material Surrounding gate MOSFET suppressed Short Channel Effect
- Analysis and Optimization of Floorplanning algorithms for VLSI Physical Design
- Design and FPGA Implementation Elliptic curve Cryptographic Processor
- Power Integrity for TSV based 3D –Integrated Circuits
- Efficient FPGA implementation of Key Components for LTE downlink Receiver
|
| Sponsored Projects |
|---|
- Setting up of EDA tools Laboratory for ASIC Design – AICTE New Delhi
- Design of W band LNA in 130nm SiGe Process – RCI (24.73 lakhs)
|
| Infrastructure created by sponsored projects |
|---|
- Xilinx FPGA Kits
- Xilinx CPLD Kits
- Digilent FPGA Boards
- V-Design RAPID ASIC
|
| Papers Published |
|---|
| International Journal - 152 |
| National Journal - 63 |
| International Conferences - 237 |
| Industries Interfaced |
|---|
- Analog Devices India Pvt. Ltd.
- Cadence Design Systems Pvt. Ltd
- Broadcom India Pvt. Ltd.
- Honeywell Technology Solutions Lab
- IBM Global Services India Pvt. Ltd.
- Motorola India Electronics Ltd.
- National Instruments India
- Siemens Semiconductors Group
- Texas Instruments India
- Wipro Technologies Pvt. Ltd.
|
| People |
|---|
- Dr S. Rajaram
- Dr N B Balamuruagan
- Dr Gracia Nirmala Rani-Lab-in-charge
- Dr V R Venkatasubramani
- Dr V Vinoth Thiagarajan
- Dr J. Shanthi
|
